Physical Design Engineer

Role: Physical Design Engineer (RTL to GDSII)

Day Rate: £600–£800/day (Inside IR35)

Location: Cambridge

Contract Length: 6 months

My client, a leading technology company working on advanced semiconductor IP, is looking for an experienced Physical Design Engineer to support the development of cutting-edge GPU technology. This is a hands-on implementation role, taking high-performance blocks from RTL through to STA, with a focus on pushing the limits of power, performance, and area (PPA) at advanced process nodes.

You’ll be part of a collaborative project team, working closely with RTL designers and tool vendors to optimise flow and meet aggressive delivery milestones.

Key Responsibilities:

• Full physical implementation from RTL to GDSII, including synthesis, floorplanning, place & route, and timing closure
• Run equivalence checking (LEC), CLP, and drive constraint development and UPF debug
• Provide structured RTL feedback via Jira and direct communication to improve PPA
• Collaborate with tool vendors to debug and optimise EDA tool performance
• Independently plan, schedule, and report on progress across multiple milestones

Key Skills & Tools:

• Cadence: Genus, Innovus, Tempus, Conformal
• Synopsys: Fusion Compiler, Formality
• RTL-to-GDSII flow: Synthesis, Floorplanning, PnR, CTS, STA, CLP
• Strong scripting skills (TCL, Python, Perl) for flow automation
• Experience with low-power techniques (e.g., power gating, DVFS)
• Prior experience on advanced nodes (N3P/N2P) highly desirable

Keywords:

RTL, STA, Physical Design, PnR, Cadence Genus, Innovus, Tempus, Synopsys Fusion, LEC, CLP, Low Power, UPF, Scripting, Python, Contract, Inside IR35, Cambridge