Physical Design Engineer
UK Visa Sponsorship Analytics
Above analytics are generated algorithmically based on job titles and may not always be the same as the company's job classification. You can also check detailed occupation eligibility, and salary criteria on our UK Visa Eligible Occupations & Salary Thresholds page.
Disclaimer: Hunt UK Visa Sponsors aggregates job listings from publicly available sources, such as search engines, to assist with your job hunting. We do not claim affiliation with Fractile Ltd. For the most up-to-date job details, please visit the official website by clicking "Apply Now."
Fractile’s mission is to enable a new chapter in the AI revolution. We’re pioneering AI innovation where hardware and software join to create something extraordinary, unlocking the power of the world’s largest language models with speed increases of x100. Our team is rapidly expanding, and we're searching for visionary engineers, scientists, and thinkers who share our passion for pushing boundaries and redefining what's possible. If you're ready to join a dynamic group of innovators shaping AI's future, we want to hear from you!
We are seeking a Physical Design Engineer to contribute to our next-generation chip designs. As a Physical Design Engineer, you will support the implementation of complex IC physical designs, from synthesis to sign-off. You will collaborate with cross-functional teams, including logic design, verification, and process technology, to optimise performance, power, and area (PPA) while ensuring design integrity and manufacturability.
Key Responsibilities:
- Support the physical implementation of ASIC/SoC designs, including floor planning, placement, clock tree synthesis (CTS), routing, and sign-off.
- Work on synthesis, timing analysis (STA), and optimisation to achieve strong PPA metrics.
- Assist in power planning and analysis, addressing IR drop, electromigration, and related effects.
- Ensure design rule check (DRC), layout vs. schematic (LVS), and other physical verification compliance.
- Collaborate with DFT engineers to integrate design-for-test (DFT) structures into the physical implementation.
- Develop flows in EDA tools such as Cadence Innovus, Synopsys Fusion Compiler, Mentor Graphics Calibre, and others.
- Work closely with RTL and architecture teams to support design feasibility, constraints, and physical-aware RTL design.
- Work with advanced AI tools and models to improve productivity, analysis, and design quality.
Preferred Qualifications:
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
- 0–5 years of experience in physical design for advanced technology nodes (e.g., 7nm, 5nm, or below), including internships.
- Familiarity with EDA tools for place & route, STA, and sign-off.
- Basic understanding of CMOS technology, semiconductor physics, and process limitations.
- Exposure to timing closure, signal integrity, IR drop analysis, and formal verification.
- Proficiency in scripting languages like TCL, Perl, or Python for automation is a plus.
- Excellent problem-solving skills, communication, and teamwork in a collaborative design environment.
- Interest in working with advanced AI tools and models as part of the design workflow.
- Experience or coursework in high-performance computing (HPC), AI accelerators, or networking chips is a plus.