Application Specific Integrated Circuit Design Engineer
Possible
Sponsorship likelihood
This employer issued few or no visas recently
£52,000
Going rate
Skilled Worker going rate
This role likely qualifies for a Skilled Worker visa
SOC 2124 (89% match) is an eligible occupation, with a going rate of £52,000, and X4 Technology is a licensed sponsor. That is our reading of the rules. Whether they issue a Certificate of Sponsorship is still their call.
This could also be SOC 2123 (Electrical engineers). We read the code off the advert, so it is our best guess, not the employer's.
New graduate or PhD holder? Pick one of the lower rates.
What each route needs for this job
| Occupation code | New entrant 70% of going rate | STEM PhD 80% of going rate | Relevant PhD 90% of going rate | Standard rate 100% of going rate |
|---|---|---|---|---|
2124 Electronics engineers Most likely code | £36,400 Clears | £41,600 Clears | £46,800 Clears | £52,000 Clears |
2123 Electrical engineers Also possible | £41,100 Clears | £47,000 Clears | £52,900 Clears | £58,700 Clears |
We use the lowest threshold across the plausible codes. Likelihood is Possible at most when the pay clears only a lower rate, or only under a less likely code. A mark is for the top of the advertised pay. How the Home Office picks the code
About the role
🚀 ASIC Design Engineer | £175K–£200K | OUTSIDE IR35 OR High Pay Permanent
📍 UK | Hybrid – up to 3 days onsite in Oxford, 2 days remote
I’m partnering with an innovative technology business working at the forefront of AI based quantum computing is seeking an experienced ASIC Design Engineer to take end-to-end ownership of a next-generation processor architecture.
This is a rare opportunity to lead the miniaturisation of a cutting-edge computing platform, shaping everything from algorithms and instruction set architecture (ISA) through to microarchitecture, tape-out and silicon bring-up.
🔧 The Role
You’ll take ownership of the ASIC architecture, translating complex workloads into an optimised hardware platform while driving critical architectural decisions across performance, power and area.
Key responsibilities include:
- System Architecture & ISA: Define system-level architecture, instruction sets and dataflow models based on workload requirements.
- Performance Modelling: Develop functional simulations and hands-on performance models using Python, C++ or equivalent to drive architectural decisions.
- Hardware/Software Co-Design: Analyse arithmetic implementation, programmability, fixed-function hardware and host-system requirements.
- Microarchitecture: Define detailed specifications covering RTL requirements, memory hierarchy, on-chip and inter-chip connectivity, and hardware/software interfaces.
- PPA Optimisation: Lead architectural partitioning and trade-off analysis across timing, power and area, with physical design awareness.
- IP & Integration: Oversee internal IP development and evaluate third-party IP.
- Silicon Delivery: Guide the design through verification strategy, sign-off, tape-out and bring-up.
🧠 What We're Looking For
- Proven architectural ownership of at least one ASIC through successful tape-out.
- Experience with compute accelerators, inference engines, DSPs or comparable processor architectures.
- Strong hands-on performance modelling and simulation skills using Python, C++ or equivalent.
- Experience with industry-standard EDA tools and flows, such as Synopsys, Cadence or Siemens.
- A solid understanding of architectural trade-offs involving timing, power and area.
- Experience defining hardware/software interfaces and working with firmware and compiler teams.
- Strong RTL design experience and the ability to define verification strategies at architectural level.
💰 Package & Working Arrangement
✅ £175,000–£200,000
✅ Outside IR35 contract or permanent employment (Permanent is preferable given the longevity of the work but if the suitable applicant is interested in contract initially it is still worth applying).
✅ Hybrid working: up to 3 days onsite and 2 days remote per week
✅ Industry Leading benefits (Available on request)
✅ Significant architectural ownership from system-level design through to silicon
Why consider it?
This is an opportunity to shape the architecture of an ambitious, next-generation probabilistic computing processor, influence fundamental design decisions and take ownership of a technology platform from initial modelling through to physical silicon.
If you’re an ASIC Architect who enjoys solving complex engineering challenges and wants to make a tangible impact on next-generation computing, I’d welcome a confidential conversation.
📩 Interested? Please apply with an up to date CV, alternatively Send me a message, or get in touch if you know someone who would be a strong fit.
#ASIC #ASICDesign #Semiconductors #ChipDesign #SiliconEngineering #HardwareArchitecture #Cplusplus #CPP #VLSI #EngineeringJobs
This description is the source posting as it read when we added it. We are not affiliated with X4 Technology, so check their own site for the current details.
Where this offer sits in the market
Electronics engineers (SOC 2124) · UK · ONS ASHE 2025 · basic pay · ~17k in sample- Middle half £41,080–63,180
- Median £48,672
- Going rate £52,000
- Threshold £41,700
- New entrant £36,400–46,800
Similar sponsored roles
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About sponsorship for this role
Does this job guarantee visa sponsorship?
Not necessarily. X4 Technology holds a sponsor licence, but sponsorship for a specific hire is always the employer's decision. Be upfront in your application that you'll require it.
What salary is needed for this role to be eligible?
The offer must clear both the general threshold and the SOC 2124 going rate of £52,000. New-entrant and shortage discounts can lower it.